Q1.
(a)
In the circuit shown below, find the ratio Io/IREF:
Assume that β = 50 and Q1 and Q2 are matched.
(b)
Obtain the NAND logic diagram of a full adder from the Boolean function
C = xy + xz + yz
S = C'(x + y + z) + xyz
where C' = NOT(C). Assume that two-input and three-input NAND gates are available.
(c)
Compute the error constants and steady-state errors for unit-step, unit-ramp and unit-parabolic inputs for a system with
G(s) = (K(s + 3.15))/(s(s + 1.5)(s + 0.5))
and H(s) = 1.