Q1.
(a)
CANDIDATE COPY ICANDIDATE COPY A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two-
1. dimensional array of size 512 × 512 with elements that occupy bytes each. Consider the following two C code segments, P1 and P2: P2: P1: ม่งสถิทิตกว่ for (i = 0; i < 512; i + + ) anound time for (i = 0; i < 512; i + + ) for (j = 0; j < 512; j + + ) for (j = 0; j < 512; j + + ) Time : 3 hours \hatm \epsilon : mπ x ← A[j][i]; x ← A[i][j]; ЭРНЭЗЧЭ ИЗЧАЧ ИОНУЛЬО 276152315142 P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2. Find M1 \mathbbH Then are friend
(15) questions in all
(b) Ratio of M2/M1. Marks An intern at Intel has designed the combinational circuit shown below. His supervisor is